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Quartus II警告及原因
my17sky | 2012-11-02 16:25:46    阅读:11324   发布文章

1、Warning (10227): Verilog HDL Port Declaration warning at PRESS_MODELE.v(29): data type declaration for "iR" declares packed dimensions but the port declaration declaration does not.

解释:

2、Warning: PLL "DE2_TV:inst1|Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|pll" output port clk[0] feeds output pin "DRAM1_CLK" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance

解释:PLL的输出用在了非专属的PLL_OUT

措施:设计电路板的时候最好将PLL_OUT用在相关的时钟信号上,如果没有使用,则这个警告不理会也可。

3、Warning: Using design file cpu.v, which is not specified as a design file for the current project, but contains definitions for 25 design units and 25 entities in project

解释:模块不是在本项目生成的,而是直接copy了别的项目的原理图和源程序生成的,不是用QUARTUS将文件添加进本项目 

措施:无须理会,不影响使用

4、Warning (10240): Verilog HDL Always Construct warning at I2C_V_Config.v(153): inferring latch(es) for variable "LUT_DATA", which holds its previous value in one or more paths through the always construct

解释:信号被综合成了latch,锁存器的EN和数据输入端口存在一个竞争的问题

措施:将计数器从里面抽出来

5、Warning: 12 hierarchies have connectivity warnings - see the Connectivity Checks report folder

解释:实例化的时候,有一些端口没用,让没用的端口的位置空着,

措施:不用理会

6、Warning: Synthesized away the following node(s)

解释:以下节点被综合优化掉

措施:不用理会

7、Warning:Found xx output pins without output pin load capacitance assignment
解释:没有给输出管教指定负载电容

措施:该功能用于估算TCO和功耗,可以不理会,也可以在Assignment Editor中为相应的输出管脚指定负载电容,以消除警告

8、Warning: The following nodes have both tri-state and non-tri-state drivers

解释:该用三态逻辑驱动的信号,被用非三态逻辑驱动了

措施:在子信息中定位到警告所在,改用三态逻辑驱动

9、Warning: Latch DE2_TV:inst1|I2C_V_Config:I2C_AV_Config|LUT_DATA[8] has unsafe behavior

Warning: Ports D and ENA on the latch are fed by the same signal DE2_TV:inst1|I2C_V_Config:I2C_AV_Config|LUT_INDEX[4]

解释:产生了latch

措施:用时序代替组合电路,或者是用完备的if/else,和case语句

10、Warning: TRI or OPNDRN buffers permanently enabled

解释:输出要加三态控制

11、Warning: Output pins are stuck at VCC or GND

解释:这几个输出管脚直接接地了

措施:如果这符合你的设计要求这种警告可以不管

12、Warning (15400): WYSIWYG primitive "DE2_TV:inst1|Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_21m1:auto_generated|altsyncram_1l81:fifo_ram|altsyncram_drg1:altsyncram5|ram_block6a15" has a port clk1 that is stuck at GND

解释:这里是采用的SDRAM的读写方式为1入2出的模式,将fifo2的输入信号给接GND了

措施:不用理会。

另外:如果出现跟RAM相关的WYSIWYG primitive错误或者是警告,则是RAM的输入端信号不通导致。

13、Warning: Design contains 2 input pin(s) that do not drive logic

解释:有2个输入没有驱动任何逻辑,也就是说,只定义了2个输入管脚,但在逻辑中并没有使用这2个输入信号

措施:将这2个输入管脚的定义去掉即可

14、Warning: At least one of the filters had some problems and could not be matched.

解释:

措施:

15、Warning: Node: XXX was determined to be a clock but was found without an associated clock assignment.

解释及措施:

(1). 这个信号是不是你期望的时钟信号?还是被综合器误将普通信号综合成了时钟信号?有没有在代码中用过这个信号的上升沿/下降沿?
(2). 如果是期望的时钟信号,那么是否有可能调整管脚位置约束到专用时钟管脚?如果不行的话,这条时钟线上的延时会比较大。但是整个布局布线还是可以进行下去的。

16、Warning: PLL "DE2_TV:inst1|Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|pll" is in normal or source synchronous mode with output clock "compensate_clock" set to clk[0] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins

解释:

措施:

17、Warning: PLL "DE2_TV:inst1|Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|pll" output port clk[0] feeds output pin "DRAM1_CLK" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance

解释:这是说没有使用FPGA专用的PLL输出引脚

措施:同2

18、Warning: Ignored locations or region assignments to the following nodes

Warning: Node "FIELD" is assigned to location or region, but does not exist in design

解释:有些引脚做了分配,但是在设计中没有使用

措施:可以不用理会

19:Warning: Following 1 pins have no output enable or a GND or VCC output enable - later changes to this

connectivity maychange fitting results

解释:下面有1个管脚没有输出使能,或者仅仅是GND,VCC使能

措施:给其配置一个使能即可

20、Warning: Following 4 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may

change fitting results

解释:同11

措施:同11

21、Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving

ground'.

解释:所有没有用到的管脚都直接接GND

措施:可以不用理会,也可以在 Assignments 里做修改

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